Electronics and Optoelectronics
Optoelectronic Semiconductor Technology
Electronic and optoelectronic packaging technology
Technology/Patent
Summary
◆The TSV process is a key technology for 3D chip stacking by providing a route with the shortest and vertical interconnection path to replace the traditional wire-bonding process in chip/wafer stacking
◆TSV technology can increase chip density, reduce form factor, enhance bandwidth, cut power consumption, and improve product performance
◆via last through silicon via technology increase 60％ system performance and reduce 70％ power consumption in SRAM and logic chip stacking
◆via middle through silicon via with 4 layers 8Gb memory chip stacking
◆Dramatically reduce the package size and increase performance by integrating BSI CIS+ADC+ISP chip stacking
Data category
Technology
Data ID
S11204I0031
Owner
Industrial Technology Research Institute(工業技術研究院)
Owner attribute
Research institution
Technology Maturity
Trial production
Sales Period (Start)
2023/04/10
Transaction method
Patent_exclusive license,Patent_non-exclusive license,Joint development,Negotiate by self,
Effective date of publication
2025/04/13